1. Field of the Invention
Embodiments of this invention relate generally to the field of computer processing and more specifically relate to managing multiple physical data paths from a host computer system to peripheral devices.
2. Description of the Related Art
Advances in computer processor architecture have resulted in increased processing speeds up to and beyond one gigahertz. One goal of computer development therefore has been directed to having tasks immediately available for these fast processors. Management of internal resources to keep the processor busy may include hardware and software multithreading registers, cache management, pipeline allocation, branch prediction, etc. The external resources may refer to external disk drives, external memory storage, printing, network communication, etc. Typically, management of data for processing along these multiple external pathways, which are usually multiple buses of various protocols to and from these attached peripheral devices, has been relegated to the host operating system and/or the host device driver software applications. Typically during processing to these peripheral devices, the host operating system executes a device driver application or function so that it can communicate with an adapter connected to the peripheral device. The system's operating system executes, for example, an application program until an interrupt or some instruction in the program indicates that a peripheral device needs data, has the required data, or otherwise requires attention. A conventional context switch procedure changes the context of the host processing system between the device driver and the application program that had been executing.
Given the increasing complexity and pervasiveness of today's computer systems and the increased reliance by the users upon these systems, the management of the physical pathways to/from a host computer system is increasingly important. There are many different pathway management protocols: PCI and PCI-X, Token Ring, Gigabyte Ethernet, Ethernet, Fibre Channel, SSA, Fiber Channel Arbitrated Loop (FCAL), Serial SCSI, Ultra3 SCSI, Infiniband, FDDI, ATM, 1394, ESCON, wireless relays, Twinax, LAN connections, WAN connections, high performance graphics, etc. It is difficult for the operating system to track and maintain the state of all these buses and their various protocols and schemes for ordering or prioritizing commands. A processor's efficiency is severely compromised if it has to manage data transfer on all these various buses at the same time. Bus protocols, moreover, are constantly evolving and moving towards industry standardization but until then connecting to a new device may involve connecting to a new bus with its own proprietary protocol.
Increasingly so in computer systems, there may be more than one physical pathway from an adapter to its peripheral or external device. One method to manage external bus traffic is to use devices with multiple ports, each port having its own I/O adapter that may or may not have a shared or unique cache and with each port having a distinct independent physical pathway to the same external device. The allocation of one pathway as the primary pathway and another or others as backup pathway(s) may be statically assigned in microcode at initialization by the host operating system or the device driver. The host operating system may be aware of the multiple pathways, or may just consider each physical path as a different device. In the latter scenario, even though one device is connected to the host computer system through a dual-ported adapter and there are two independent physical paths to device, the host operating system sees two devices with the same name. In any event, to change or reroute data from the primary to the backup path, the host computer's operating system becomes involved.
The host operating system may have difficulty maintaining cache coherency of adapter caches if there is a separate cache in the adapter for each pathway to the same device. For example, imagine that the host wants to access an external memory device having independent physical paths each with its own adapter. The cache associated with one physical path may have an outstanding WRITE command that hasn't been executed but before it can write the fresh data to the memory location in the peripheral device, a READ command that actually issued after the WRITE command accesses that memory location on the other path and obtains undetected stale data. Because the problem is undetected, no error is generated.